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# SRAM and DRAM
## ...but mostly review

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CS 130 // 2021-11-17

## Administrivia
- Assignment 5 due on Wednesday

# Exam 3
- Monday, November 22nd

## Exam 3
- **Format of the exam**:
    + Written, in-class, 75-minute exam
    + Closed textbook/notes/internet
    + Can bring a 8.5 x 11, single-sided "cheat sheet"
- 
 **Topics**:
    + Logic gates, truth tables, Boolean algebra, combinatorial logic, sequential logic
- 
 Some of Wednesday will be dedicated to practice problems, prepping for the exam

# Questions
## ...about anything?

# Memory

## Sequential Logic
- **Sequential** logic circuits do have memory
    + 
 Output depends on both the input and current state of memory
    + 
 Behavior can change **over time**

### Sequential Logic Components
- **Clock**: a signal that oscillates between 0 and 1
- 
 **Latch**: 1-bit memory element that is updated when the clock is 1
- 
 **Flip Flop**: 1-bit memory element that is updated when the clock transitions from a 1 to a 0
- 
 **Register**: multi-bit memory unit (32 or 64 bits) that consists of an array of flip flops or latches
- 
 **Register Files**: An array of registers

## S-R Latch
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- A "set reset" latch is implemented with
    <img src='/teaching/2021f/cs130/assets/images/COD/sr-latch.png' alt="S-R latch diagram" />

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## D Latch
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- A "data" latch is implemented with
    <img src='/teaching/2021f/cs130/assets/images/COD/d-latch.png' alt="D latch diagram" />

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# SRAM / DRAM

## Static Random Access Memory
- Memory where data is stored *statically* with flip-flops
- Faster than DRAM but less dense (lower capacity) and more expensive per bit
- As long as it has power, SRAM will keep its value
- Usually used for cache memory

## Dynamic Random Access Memory
- DRAM is the most dense of RAM
    * Implemented with capacitors instead of latches
- Must be occasionally "refreshed" because the capacitors slowly lose their stored values
    * This is why it is called "dynamic"
- Usually used for large capacity RAM

# Exam Review